With advances in computing technology, computing devices are smaller and have much more processing power. Additionally, they include more and more storage and memory to meet the needs of the programming and computing performed on the devices. The shrinking size of the devices together with the increased storage capacity is achieved by providing devices with higher density, where there are more and more atomic storage units within a memory device, but each has smaller and smaller geometries.
Within the latest generation of increased density devices, intermittent failure has appeared in some devices. For example, some existing DDR3 (dual data-rate, version 3) based systems experience intermittent failures with heavy workloads. Researchers have traced the failures to repeated access to a single row of memory within the refresh window of the memory cell. For example, for a 32 nm process, if a row is accessed 550K times or more in the 64 ms refresh window, the physically adjacent wordline to the accessed row has a high probability of experiencing data corruption. The condition has been referred to as “row hammer” or “single row disturb” in the DRAM (dynamic random access memory) industry, where the condition is most frequently observed. The row hammering can cause migration across the passgate. The leakage and parasitic currents caused by the repeated access to one row cause data corruption in a non-accessed physically adjacent row.
One approach identified to deal with the failure due to row hammer is to limit the number of accesses allowed per row per refresh cycle, which has performance impacts in the system. Another approach identified to address the row hammer failure includes decreasing the bottom critical dimension (BCD) in the buried channel array transistor (BCAT), and/or increasing channel length to improve the drain induced barrier lowering (DIBL). However, changing the dimension sizes of the devices has both physical and practical limitations. To the extent certain dimensions may now be changed, it would still require changes to the manufacturing processes. Also, it leaves open the question of how to address the issue in next-generation products.
Another approach to dealing with the row hammer issue is to decrease the time between refreshes. However, the refresh time has already been held constant even as the density of the devices has increased. Current devices are required to perform refresh on larger and larger areas in the same period of time. Thus, further decreasing the refresh time would cause a performance impact in the system, such as by requiring additional refresh overhead in the memory devices.
Thus, the approaches that attempt to prevent the row hammer condition by device design or changes to the operating parameters have significant limitations. However, detecting the row hammer condition in an operating device presents other challenges.
Descriptions of certain details and implementations follow, including a description of the figures, which may depict some or all of the embodiments described below, as well as discussing other potential embodiments or implementations of the inventive concepts presented herein.